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Freescale Semiconductor Technical Data
MC100ES8111 Rev 2, 09/2004
Low Voltage 1:10 Differential HSTL Clock Fanout Buffer
The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Features * * * * * * * * * 1:10 differential clock fanout buffer 80 ps maximum device skew SiGe technology Supports DC to 625 MHz operation of clock or data signals HSTL compatible differential clock outputs PECL and HSTL compatible differential clock inputs 3.3 V power supply for device core, 1.5 V or 1.8 V HSTL output supply Supports industrial temperature range Standard 32 lead LQFP package
MC100ES8111
LOW-VOLTAGE 1:10 DIFFERENTIAL HSTL CLOCK FANOUT BUFFER
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03
Functional Description The MC100ES8111 is designed for low skew clock distribution systems and supports clock frequencies up to 625 MHz. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential HSTL compatible outputs. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 10 outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The HSTL compatible output levels are generated with an open emitter architecture. This minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 DC termination to GND (0 V). The output supply voltage can be either 1.5 V or 1.8 V, the core voltage supply is 3.3 V. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm 2 32-lead LQFP package.
(c) Freescale Semiconductor, Inc., 2004. All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary
Q3
Q4
Q4
Q5
Q5
Q6 18
VCC CLK0 CLK0
0
VCC CLK1 CLK1
1
OE
CLK_SEL
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9
24 VCCO Q2 Q2 Q1 Q1 Q0 Q0 VCCO 25 26 27 28 29 30 31 32 1
23
22
21
20
19
Q6 17 16 15 14 13 VCC0 Q7 Q7 Q8 Q8 Q9 Q9 VCCO 12 11 10 9 8 GND
Q3
MC100ES8111
2
3
4
5
6
7
VCC
CLK_SEL
CLK0
CLK0
OE
CLK1
OE
Figure 1. MC100ES8111 Logic Diagram Table 1. Pin
Pin CLK0, CLK0 CLK1, CLK1 CLK_SEL OE Q[0-9], Q[0-9] GND VCC VCCO
Figure 2. 23-Lead Package Pinout (Top View)
Configuration(1)
I/O Input Input Input Input Output Supply Supply Supply HSTL PECL LVCMOS LVCMOS HSTL Type Function Differential HSTL reference clock signal input Differential PECL reference clock signal input Reference clock input select Output enable/disable. OE is synchronous to tlhe input reference clock which eliminates possible output runt pulses when the OE state is changed. Differential clock outputs Negative power supply Positive power supply of the device core (3.3 V) Positive power supply of the HSTL outputs. All VCCO pins must be connected to the positive power supply (1.5 V or 1.8 V) for correct DC and AC operation.
1. Input pull-up/pull-down resistors have a value of 75 k.
Table 2. Function Table
Control CLK_SEL OE Default 0 0 0 CLK0, CLK0 (HSTL) is the active differential clock input Q[0-9], Q[0-9] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses. 1 CLK1, CLK1 (PECL) is the active differential clock input Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses.
MC100ES8111 2 Freescale Confidential Proprietary NDA Required / Preliminary Advanced Clock Drivers Device Data Freescale Semiconductor
CLK1
Table 3. Absolute Maximum Ratings(1)
Symbol VCC VCCO VIN VOUT IIN IOUT TS TFunc Supply Voltage Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Functional Temperature Range -65 TA = -40 Characteristics Min -0.3 -0.3 -0.3 -0.3 Max 3.6 3.1 VCC + 0.3 VCC + 0.3 20 50 125 TJ = +110 Unit V V V V mA mA C C Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 4. General Specifications
Symbol VTT MM HBM CDM LU CIN JA Characteristics Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) ESD Protection (Charged device model) Latch-up Immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board 200 2000 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ 0 Max Unit V V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition
JESD 51-6, 2S2P multilayer test board
JC TJ
Thermal Resistance Junction to Case Operating Junction Temperature(1) (continuous operation)MTBF = 9.1 years
110
C
1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this datasheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES8111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES8111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
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Table 5. DC Characteristics (VCC = 3.3 V 5%, VCCO = 1.5 V 0.1 V or VCCO = 1.8 V 0.1 V), TJ = 0C to +110C
Symbol Characteristics Min Typ Max Unit Condition Clock Input Pair CLK0, CLK0 (HSTL differential signals) VDIF VX, IN VIH VIL IIN Differential Input Voltage(1) Differential Cross Point Input High Voltage Input Low Voltage Input Current Voltage(2) 0.2 0.25 VX+0.1 VX-0.1 150 0.68 - 0.9 VCC-1.3 V V V V A VIN = VX 0.1 V
Clock Input Pair CLK1, CLK1 (PECL differential signals) VPP VCMR VIH VIL IIN Differential Input Voltage(3) Differential Cross Point Input Voltage High Input Voltage Low Input Current Voltage(4) 0.15 1.0 VCC-1.165 VCC-1.810 1.0 VCC-0.6 VCC-0.880 VCC-1.475 150 V V V V A VIN = VIH or VIN Differential operation Differential operation
LVCMOS Control Inputs OE, CLK_SEL VIL VIH IIN Input Voltage Low Input Voltage High Input Current 2.0 150 0.8 V V A VIN = VIH or VIN
HSTL Clock Outputs (Q[0-9], Q[0-9]) VX, OUT VOH VOL Output Differential Crosspoint Output High Voltage Output Low Voltage 0.68 1.0 0.4 0.75 0.9 V V V
Supply Current ICC ICCO(5) Maximum Supply Current without output termination current Maximum Supply Current, outputs terminated 50 to VTT 80 350 105 410 mA mA VCC pin (core) VCCO pins (outputs)
1. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 2. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 5. ICC includes current through the output resistors (all outputs terminated to VTT). See also "Power Consumption and Junction Temperature" on page 6.
MC100ES8111 4 Freescale Confidential Proprietary NDA Required / Preliminary Advanced Clock Drivers Device Data Freescale Semiconductor
Table 6. AC Characteristics (VCC = 3.3 V 5%, VCCO = 1.5 V 0.1 V or VCCO = 1.8 V 0.1 V), TJ = 0C to +110C(1)
Symbol VDIF VX, IN fCLK tPD tSK(PP) tSK(P) Characteristics Differential Input Voltage(2) (Peak-to-Peak) Differential Cross Point Voltage(3) Input Frequency Propagation Delay CLK0 to Qn Output-to-Output Skew (Part-to-Part) Output Pulse Skew(4) VCCO = 1.8 V VCCO = 1.5 V VCCO = 1.8 V VCCO = 1.5 V VCCO = 1.8 V VCCO = 1.5 V 0.2 1.0 0 VCCO = 1.8 V VCCO = 1.5 V VCCO = 1.8 V VCCO = 1.5 V VCCO = 1.8 V VCCO = 1.5 V 0.68 VCCO = 1.8 V VCCO = 1.5 V VCCO-0.8 V VCCO-0.5 V 0.2 0.45 0.40 37 60 150 2.5*T + tPD 3.0*T + tPD 0.91 590 590 860 910 Min 0.4 0.68 0 700 700 990 1030 0.9 625 1270 1420 570 720 100 150 1.0 VCC-0.6 625 1220 1360 630 770 150 200 1.1 1.5 1.5 0.8 1.0 1.0 80 105 1.0 800 3.5*T + tPD 4.0*T + tPD Typ Max Unit V V MHz ps ps ps ps ps ps V V MHz ps ps ps ps ps ps V V V V V V ps ps ps ps ns ns 20% to 80% T=CLKn period T=CLKn period Differential Differential Differential Differential Differential Differential Condition REF_SEL= 0, Active Clock Input Pair CLK0, CLK0 (HSTL differential signals)
REF_SEL = 1, Active Clock Input Pair CLK1, CLK1 (PECL differential signals) VPP VCMR fCLK tPD tSK(PP) tSK(P) Differential Input Voltage(5) (Peak-to-Peak) Differential Input Crosspoint Voltage(6) Input Frequency Propagation Delay CLK1 to Qn Output-to-Output Skew (Part-to-Part) Output Pulse Skew(7)
HSTL Clock Outputs (Qn, Qn) VX, OUT VOH VOL VO(P-P) tSK(O) tJIT(CC) tr, tf tPDL(8) tPLE(9) Output Differential Crosspoint Output High Voltage Output Low Voltage Differential Output Voltage (Peak-to-Peak) VCCO = 1.8 V VCCO = 1.5 V Output-to-Output Skew Output Cycle-to-Cycle Jitter RMS (1 ) Output Rise/Fall Time Output Disable Time Output Enable Time VCCO = 1.8 V VCCO = 1.5 V
1. AC characteristics apply for parallel output termination of 50 to VTT (GND). 2. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VDIF (DC) specification. 4. Output duty cycle is DC = (0.5 150 ps * fOUT) * 100%. E.g. the DC range at fOUT = 100 MHz is 48.5% < DC < 51.5%. 5. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 6. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. The output duty cycle is DC = (0.5 200 ps * fOUT) * 100%. E.g. the DC range at fOUT = 100 MHz and VCCO = 1.5 V is 48.0% < DC < 52.0%. 8. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). 9. Propagation delay OE assertion to output enabled (active).
MC100ES8111 Advanced Clock Drivers Device Data Freescale Semiconductor Freescale Confidential Proprietary NDA Required / Preliminary 5
APPLICATIONS INFORMATION
Test Reference and Output Termination The MC100ES8111 is designed for high-frequency and low-skew clock distribution. The high-speed differential outputs are capable of driving 50 transmission lines and always require a DC termination to VTT (GND). In order to maintain the tight skew and timing specifications, it is recommend to terminate the differential outputs by 50 to
VCC = 3.3 V 5% VCCO = 1.8 V 0.1 V or 1.5 V 0. 1 V
GND, with the termination resistor located as close as possible to the end of the clock transmission line. All DC and AC specifications apply to this termination method (see the reference circuit shown in Figure 3 "MC100ES8111 AC Test Reference"). The MC100ES8111 does not support an output termination to VTT = VX = 0.75 V (center voltage termination).
Differential Pulse Generator Z = 50
Z = 50
Z = 50
Oscilloscope or Tester
RT = 50 VTT = GND
DUT MC100ES8111
RT = 50 VTT = GND
Figure 3. MC100ES8111 AC Test Reference Power Consumption and the Junction Temperature The power consumption PTOT of the MC100ES8111 depends on the supply voltages and the DC output termination. The clock frequency has a negligible effect on PTOT. If all outputs are terminated by 50 to GND, the device power consumption is calculated by: PTOT = VCC * ICC + ICCO * (VCCO - VX) For instance, at a supply voltage of VCC = 3.3 V and a termination of 50 to GND, the typical device power consumption is 579 mW at VCCO = 1.8 V and 474 mW at VCCO = 1.5 V. Table 7. Power Consumption
MC100ES8111 VCCO = 1.5 V VCCO = 1.8 V PTOT, TYP(1) 470 mW 575 mW PTOT, MAX(2) 647 mW 769 mW
typical power consumption of 575 mW (all outputs terminated 50 ohms to GND, VCCO = 1.8 V), the junction temperature of the MC100ES8111 is approximately TA + 31C, and the minimum ambient temperature in this example case calculates to -31C (the maximum ambient temperature is 79C. See Table 8). Exceeding the minimum junction temperature specification of the MC100ES8111 does not have a significant impact on the device functionality. However, the continuous use the MC100ES8111 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Table 8. Ambient Temperature Ranges (Ptot = 575 mW)
Rthja (2s2p board) Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0C/W 54.4C/W 52.5C/W 50.4C/W 47.8C/W TA, min(1) -34C -31C -30C -29C -27.5C TA, max 76C 79C 80C 81C 82.5C
1. Typical case: VCC, VCCO at nominal values and using typical ICC, ICCO data. 2. Worst case: VCC, VCC at max. values and using max. ICC, ICCO limits.
To make the optimum use of high clock frequency and low skew capabilities of the MC100ES8111, the device is specified, characterized and tested for the junction temperature range of TJ = 0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this datasheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja * Ptot Assuming a thermal resistance (junction to ambient) of 54.4C/W (2s2p board, 100 ft/min airflow, see Table 8) and a MC100ES8111 6
1. The MC100ES8111 device function is guaranteed from TA = -40C to TJ = 110C.
Maintaining Lowest Device Skew The MC100ES8111 guarantees low output-to-output skew of max. 80 ps and a part-to-part skew of max. 630 ps (VCCO = 1.8 V). To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all ten output pairs are used, identical termination of all output pairs within the output bank (same package side) is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew.
Freescale Confidential Proprietary NDA Required / Preliminary
Advanced Clock Drivers Device Data Freescale Semiconductor
Power Supply Bypassing The MC100ES8111 is a mixed analog/digital product. The differential architecture of the MC100ES8111 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
Output Enable/Disable Control The MC100ES8111 enables and disables outputs synchronously to the input clock signal. The user may enable and disable the outputs by using the OE control regardless of any hold and setup time constraints. Output runt pulses are prevented in any case. Outputs are disabled in logic low state (Qn=Low, Qn=High) without a change of the output impedance.
3.3 V 5% 33...100 nF 1.8 V 0.1 V or 1.5 V 0. 1V 0.1 nF
VCC
MC100ES8111
4 33...100 nF 0.1 nF
VCCO
Figure 4. VCC, VCCO Power Supply Bypass
CLKn CLKn
50% OE tPDL (OE to Qn) tPLE (OE to Qn) Outputs Disabled
Qn Qn
Figure 5. MC100ES8111 Output Disable/Enable Timing
MC100ES8111 Advanced Clock Drivers Device Data Freescale Semiconductor Freescale Confidential Proprietary NDA Required / Preliminary 7
AC MEASUREMENT REFERENCES
CLK0 CLK0 Qn Qn tPD (CLK0 to Qn) REF_SEL = 0 VOH VX;OUT VOL QN tSK(O) Q0 VDIF = 1.0 V VX,IN = 0.75 V Q0 QN VO(P-P)
Figure 8. Output-to-Output Skew The output-to-output skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device.
Figure 6. MC100ES8111 AC Reference Measurement Waveform (HSTL Input)
CLK1 CLK1 Qn Qn tPD (CLK1 to Qn) REF_SEL = 1 VOH VX;OUT VOL
VPP = 0.8 V
VCMR = VCC-1.3 V 80% VO(PP)
VO(P-P)
20% tR tF
Figure 9. HSTL Output Rise/Fall Time Figure 7. MC100ES8111 AC Reference Measurement Waveform (PECL Input)
MC100ES8111 8 Freescale Confidential Proprietary NDA Required / Preliminary Advanced Clock Drivers Device Data Freescale Semiconductor
PACKAGE DIMENSIONS
CASE 873A-03 ISSUE B
4X
6 D1
PIN 1 INDEX
0.20 H
A-B D e/2 3 A, B, D
D1/2
32 25
1
E1/2 A 6 E1
DETAIL G 8
B E E/2 4
F
F
17
DETAIL G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP.
7
9
D D 4
D/2
4X
0.20 C
A-B D
H
28X
e
32X
0.1 C
SEATING PLANE
C
DETAIL AD
PLATING BASE METAL
b1 c c1
b
8X
5
8
(1)
R R2 R R1
0.20
M
C A-B D
SECTION F-F
A
A2
0.25
GAUGE PLANE
A1
(S) (L1)
L
DETAIL AD
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0 7 12 REF 0.08 0.20 0.08 --0.20 REF
MC100ES8111 Advanced Clock Drivers Device Data Freescale Semiconductor Freescale Confidential Proprietary NDA Required / Preliminary 9
NOTES
MC100ES8111 10 Freescale Confidential Proprietary NDA Required / Preliminary Advanced Clock Drivers Device Data Freescale Semiconductor
NOTES
MC100ES8111 Advanced Clock Drivers Device Data Freescale Semiconductor Freescale Confidential Proprietary NDA Required / Preliminary 11
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004. All rights reserved. MC100ES8111 Rev. 2 09/2004

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